HDL Language Overviews

A working-level guide to the language: structure, types, operators, procedural code, hierarchy, patterns, testbenches and pitfalls.

1. Introduction

Verilog is a hardware description language for modeling, simulating and synthesizing digital circuits. Its syntax resembles C, and a design is organized into modules. This guide covers the whole language at a working level: structure, data types, operators, procedural code, hierarchy, common design patterns, testbenches and pitfalls.

Typical design flow

• Write modules and a testbench for each.
• Simulate to check behavior.
• Synthesize the synthesizable subset into gates and registers.
• Implement for the FPGA or ASIC target and verify timing.

Two ideas underpin everything else

Hardware is parallel: every assign and every always block is active at the same time. Non-blocking assignments model registers: all right-hand sides are sampled first, then all updates happen together.

2. Lexical elements

Compiler directives

3. Program structure

Module skeleton

module name #(
    parameter WIDTH = 8                  // compile-time parameter
) (
    input  wire             clk,         // ANSI-style port list
    input  wire [WIDTH-1:0] din,
    output reg  [WIDTH-1:0] dout
);
    // declarations: wire, reg, localparam, integer, functions, tasks
    // statements:   assign, always, initial, instances, generate
endmodule

Port directions

parameter values can be overridden at instantiation. localparam cannot be overridden and is used for internal constants such as state codes.

4. Data types

A reg is a data type, not always a register

A reg assigned in a combinational always @* block synthesizes to logic, not a flip-flop. integer is a 32-bit signed variable, useful for loop counters.

Declarations

wire              enable;        // 1-bit net
wire [7:0]        data_bus;      // 8-bit vector, bit 7 is MSB
reg  [3:0]        count;         // 4-bit variable
reg signed [7:0]  delta;         // signed vector
reg  [7:0]        mem [0:255];   // memory: 256 words of 8 bits
integer           i;             // loop counter
localparam IDLE = 2'd0, RUN = 2'd1, DONE = 2'd2;

Bit-select, part-select and concatenation

data_bus[3]            // one bit
data_bus[7:4]          // part select (constant range)
data_bus[i +: 4]       // indexed part select: 4 bits starting at i
{a, b}                 // concatenation
{4{1'b1}}              // replication: 4'b1111
{{4{sign}}, value}     // sign-extension pattern

5. Operators

Listed from highest precedence to lowest.

Note the difference between bitwise (&, works on each bit) and logical (&&, treats each operand as true or false). The reduction form &x ANDs all bits of x into one bit. === and !== are primarily used in simulation/testbenches; synthesis support is tool-dependent, so do not rely on them for portable RTL.

6. Continuous and procedural code

Continuous assignment

assign y   = a & b;                 // combinational logic on a wire
assign sum = a + b;
assign out = sel ? in1 : in0;       // 2-to-1 multiplexer

Procedural blocks

Blocking versus non-blocking assignment

Rule of thumb

Use <= in always @(posedge clk) blocks and = in always @* blocks, and never mix the two styles in one block.

Combinational and sequential blocks

// Combinational
always @* begin
    y = 1'b0;                  // default value prevents a latch
    if (en) y = a;
end

// Sequential, synchronous reset
always @(posedge clk) begin
    if (rst) q <= 8'd0;
    else     q <= d;
end

// Sequential, asynchronous reset
always @(posedge clk or posedge rst) begin
    if (rst) q <= 8'd0;
    else     q <= d;
end

Control statements

if (a) ... else if (b) ... else ...

case (opcode)
    2'b00:   result = a + b;
    2'b01:   result = a - b;
    default: result = 8'd0;
endcase

casez (req)                         // ? matches 0, 1 or z
    4'b1???: grant = 2'd3;
    4'b01??: grant = 2'd2;
    default: grant = 2'd0;
endcase

for (i = 0; i < 8; i = i + 1) parity = parity ^ data[i];
// also: while (cond) ...;  repeat (n) ...;  forever ...;

Timing controls (simulation only)

#10 clk = ~clk;              // delay
@(posedge clk);              // wait for an event
wait (done == 1'b1);         // wait for a condition

Functions and tasks

function [3:0] add_sat;          // saturating 4-bit add
    input [3:0] a, b;
    reg   [4:0] sum;
    begin
        sum     = a + b;
        add_sat = sum[4] ? 4'hF : sum[3:0];
    end
endfunction
// $clog2(n) (Verilog-2005) gives the address width for n entries

7. Hierarchy and parameterization

// Instantiate with named connections and a parameter override
up_counter #(.WIDTH(4)) u_cnt (
    .clk (clk),
    .rst (rst),
    .en  (en),
    .q   (count)
);

// Replicate hardware with generate
genvar i;
generate
    for (i = 0; i < 8; i = i + 1) begin : gen_bits
        dff u_dff (.clk(clk), .d(d[i]), .q(q[i]));
    end
endgenerate

Prefer named port connections (.port(signal)) over positional ones. Give generate blocks and instances meaningful labels.

8. Common design patterns

Counter with enable and synchronous reset

module up_counter #(parameter WIDTH = 8) (
    input  wire             clk, rst, en,
    output reg  [WIDTH-1:0] q
);
    always @(posedge clk) begin
        if (rst)     q <= {WIDTH{1'b0}};
        else if (en) q <= q + 1'b1;
    end
endmodule

Finite state machine

localparam [1:0] IDLE = 2'd0, RUN = 2'd1, DONE = 2'd2;
reg [1:0] state, next_state;

always @(posedge clk) begin           // state register
    if (rst) state <= IDLE;
    else     state <= next_state;
end

always @* begin                       // next-state logic
    next_state = state;
    case (state)
        IDLE:    if (start)  next_state = RUN;
        RUN:     if (finish) next_state = DONE;
        DONE:    next_state = IDLE;
        default: next_state = IDLE;
    endcase
end

assign busy = (state == RUN);         // output decode

Memory (inferred RAM)

reg [7:0] ram [0:255];

always @(posedge clk) begin
    if (we) ram[addr] <= din;
    dout <= ram[addr];                // registered read
end

9. Testbenches

A testbench is a module with no ports. It instantiates the design under test, generates a clock, applies stimulus from an initial block and checks the results.

Minimal testbench

`timescale 1ns/1ps
module up_counter_tb;
    reg        clk = 1'b0;
    reg        rst = 1'b1;
    reg        en  = 1'b0;
    wire [3:0] q;

    up_counter #(.WIDTH(4)) dut (.clk(clk), .rst(rst), .en(en), .q(q));

    always #5 clk = ~clk;                      // 100 MHz clock

    initial begin
        #20 rst = 1'b0;
        en = 1'b1;
        #100;
        if (q == 4'd0) $display("FAIL: counter did not count");
        else           $display("PASS");
        $finish;
    end
endmodule

Common system tasks

10. Synthesis guidance and pitfalls

11. Quick reference

12. Standards and further reading

• IEEE Std 1364-2005 (Verilog HDL), superseded by IEEE Std 1800-2009, which merged the Verilog and SystemVerilog standards into the unified IEEE 1800 family.
• Clifford Cummings (Sunburst Design) papers on blocking versus non-blocking assignments and synthesis coding styles.
• Vendor synthesis guides, for example AMD Vivado UG901, for tool-specific coding rules.

A working-level guide: data types, operators, design constructs, patterns, verification features and the synthesizable subset.

1. Introduction

SystemVerilog is an extension of Verilog that improves how hardware is described and adds a full set of features for verification. It is standardized as IEEE 1800 and is now the main language for chip verification. This guide covers the whole language at a working level: data types, operators, design constructs, interfaces, packages, classes, randomization, assertions, coverage and the synthesis subset.

Two halves of one language

Tool support varies

Support for the synthesizable subset differs by vendor, so check your synthesis tool documentation before relying on a newer construct in RTL.

2. Lexical elements

3. Data types

Built-in types

Two-state types hide problems

Two-state types cannot hold x or z. They are efficient in testbenches but can hide uninitialized values, so use logic for design signals.

User-defined types

Enums, structs and unions

typedef enum logic [1:0] {IDLE, RUN, DONE} state_t;   // enumeration

typedef struct packed {                                // packed struct
    logic [7:0] addr;
    logic [7:0] data;
    logic       write;
} bus_cmd_t;

typedef union packed {                                 // packed union
    logic [15:0]      word;
    logic [1:0][7:0]  bytes;
} word_u;

state_t   state;
bus_cmd_t cmd;
// field access: cmd.addr, cmd.write
// enum methods: state.next(), state.prev(), state.name(), state.num()

Arrays

Casting

int n = int'(3.7);                          // static cast: value 4
logic [7:0] b = 8'(n);                      // size cast
state_t s;
if (!$cast(s, 2'd1)) $error("bad state");   // dynamic cast, checks legality

4. Operators

All Verilog operators are available (see the Verilog guide for the precedence table). SystemVerilog adds the following.

5. Design constructs

Procedural blocks with declared intent

Typed blocks

always_comb begin
    y = '0;                              // default assignment
    if (en) y = a;
end

always_ff @(posedge clk)
    if (rst) q <= '0;
    else     q <= d;

always_ff @(posedge clk or negedge rst_n)   // asynchronous reset
    if (!rst_n) q <= '0;
    else        q <= d;

unique and priority

unique case asserts that no more than one case item matches and reports a violation if no item matches; priority case selects the first matching item and reports a violation if no item matches. Simulators report diagnostics when the stated uniqueness/priority assumptions are violated, and synthesis tools may use them.

Control flow

for (int i = 0; i < 8; i++) parity ^= data[i];   // loop variable declared inline
foreach (arr[i]) sum += arr[i];                  // iterate over array
do begin ... end while (cond);                   // also: break, continue, return

function automatic int max2 (int a, int b);
    return (a > b) ? a : b;
endfunction

Packages

package defs_pkg;
    localparam int BUS_W = 16;
    typedef enum logic [1:0] {IDLE, RUN, DONE} state_t;
endpackage

module wrapper
    import defs_pkg::*;                  // or refer to defs_pkg::BUS_W
(
    input  logic             clk,
    input  logic [BUS_W-1:0] din,
    output logic [BUS_W-1:0] dout
);
    always_ff @(posedge clk) dout <= din;
endmodule

Parameters and connections

module fifo #(parameter int DEPTH = 16, parameter type T = logic [7:0]) (...);

up_counter #(.WIDTH(4)) u_cnt  (.clk, .rst, .en, .q(count));   // .name shorthand
up_counter #(.WIDTH(4)) u_cnt2 (.*);                            // connect by matching names

Interfaces

An interface bundles related signals so they can be passed around as one item. A modport defines the direction of the signals as seen by each user.

interface bus_if (input logic clk);
    logic        valid, ready;
    logic [7:0]  data;
    modport master (output valid, data, input  ready);
    modport slave  (input  valid, data, output ready);
endinterface

module producer (bus_if.master bus);
    always_ff @(posedge bus.clk) if (bus.ready) bus.valid <= 1'b1;
endmodule

// top:  bus_if b_if (clk);   producer u_p (.bus(b_if));

Generate

for (genvar i = 0; i < 8; i++) begin : gen_bits
    dff u_dff (.clk, .d(d[i]), .q(q[i]));
end

6. Common design patterns

Counter

module up_counter #(parameter int WIDTH = 8) (
    input  logic             clk, rst, en,
    output logic [WIDTH-1:0] q
);
    always_ff @(posedge clk) begin
        if (rst)     q <= '0;
        else if (en) q <= q + 1'b1;
    end
endmodule

Finite state machine

typedef enum logic [1:0] {IDLE, RUN, DONE} state_t;
state_t state, next_state;

always_ff @(posedge clk) begin
    if (rst) state <= IDLE;
    else     state <= next_state;
end

always_comb begin
    next_state = state;
    unique case (state)
        IDLE: if (start)  next_state = RUN;
        RUN:  if (finish) next_state = DONE;
        DONE: next_state = IDLE;
    endcase
end

assign busy = (state == RUN);

Memory

logic [7:0] ram [256];                    // unpacked array, size 256 shorthand

always_ff @(posedge clk) begin
    if (we) ram[addr] <= din;
    dout <= ram[addr];
end

7. Verification features

Testbench structure

module up_counter_tb;
    logic       clk = 0, rst = 1, en = 0;
    logic [3:0] q;

    up_counter #(.WIDTH(4)) dut (.*);

    always #5 clk = ~clk;

    initial begin
        repeat (2) @(posedge clk);
        rst <= 0;  en <= 1;
        repeat (5) @(posedge clk);
        assert (q != 0) else $error("counter did not count");
        $finish;
    end
endmodule

Classes and randomization

Classes give object-oriented structure for reusable testbench components. Variables marked rand receive random values when randomize() is called, subject to constraint blocks. Classes also support inheritance (extends), virtual methods for polymorphism, and randc for cyclic random values.

class packet;
    rand bit [7:0] addr;
    rand bit [7:0] data;

    constraint c_addr { addr inside {[8'h10:8'h1F]}; }

    function void show();
        $display("addr=%0h data=%0h", addr, data);
    endfunction
endclass

module tb;
    packet p;
    initial begin
        p = new();
        repeat (3) begin
            if (!p.randomize()) $error("randomize failed");
            p.show();
        end
    end
endmodule

Assertions

// Immediate assertion: checked when the statement executes
assert (dout == expected) else $error("mismatch");

// Concurrent assertion (SVA): checked over clock cycles
property req_then_ack;
    @(posedge clk) disable iff (rst) req |-> ##[1:4] ack;   // ack within 1 to 4 cycles of req
endproperty
assert property (req_then_ack) else $error("ack missing");
cover  property (req_then_ack);

Functional coverage

covergroup cg @(posedge clk);
    coverpoint state;                    // was every state visited?
    coverpoint addr {
        bins low  = {[0:127]};
        bins high = {[128:255]};
    }
endgroup

cg cov = new();

Concurrency and communication

UVM

UVM is a class library and methodology built in SystemVerilog. It defines a standard testbench architecture so components can be reused across projects.

8. Synthesis guidance and pitfalls

9. Quick reference

10. Standards and further reading

• IEEE Std 1800 (SystemVerilog Language Reference Manual); current edition IEEE 1800-2023.
• IEEE Std 1800.2-2020 (UVM); also adopted as IEEE/IEC 62530-2:2023.
• Accellera Systems Initiative resources on UVM and SystemVerilog.
• Vendor documentation for the synthesizable subset supported by your tools.